iT8500E Preliminary datasheet
Digital single-phase BLDC motor driver
The iT8500E is a highly integrated single-phase BLDC motor driver combining an embedded Hall sensor, gate driver, power MOSFETs, and digital control logic into a single DFN3×3-8L chip. It introduces analog VSP speed control, 4-point speed curve, programmable lead/lag angle, and ACC/DEC slope control — significant advances over the previous generation.
The iT8500E at a glance
Power, control, protection and programming
- Wide VCC range 3.2–18V (max 22V)
- Continuous output up to 0.6A, peak 1.2A
- VSP analog input 0–3.3V for analog speed control
- PWM input 100Hz–100kHz, duty 0–100%
- Embedded Hall sensor ±15G (external Hall also supported)
- Programmable FG/RD diagnostics output
- Selectable open loop or closed loop control
- 4-point flexible speed curve setting
- ACC / DEC slope control — programmable to 2.66 / 5.33 / 7.98 / 10.64s
- Programmable lead / lag angle (fixed or linear)
- ZCD for anti-BEMF improvement
- Soft start & kick start mechanisms
- 16-point editable driving waveform
- OCP (latch) — threshold 1.65A or 2× current limit
- OVP — triggers at 24V, releases below 23V
- UVP — locks out below 8V, auto-recovers
- TSD — two selectable modes: 150°C or 175°C shutdown
- Programmable rotor lock detection: 0.25s / 0.5s
- Lock recovery retry: 0 / 1.5 / 3 / 6s programmable
- Programmable current limit: 0.10–1.65A in 0.05A steps
- iNGUI software for rapid motor parameter tuning
- I²C interface for OTP programming (PWM/SCL, FG/SDA pins)
- 2-bank OTP memory — configurable default operating code
- Pole count, lead angle, target speed, PWM duty all configurable
- Power saving mode — enters after 10ms PWM low
- FG output: 0.5×, 1.0×, or 2.0× Hall signal frequency
Pin assignment and protections
Pin assignment
| Pin | Symbol | Description |
|---|---|---|
| 1 | VSS | Ground pin |
| 2 | OUT1 | Driving motor output |
| 3 | HALL_IN | External Hall IC signal input |
| 4 | PWM/SCL | Direct PWM input / I²C SCL |
| 5 | FG/SDA | Speed signal output / I²C SDA |
| 6 | NC | No connection |
| 7 | VCC | Power supply pin |
| 8 | OUT2 | Driving motor output |
| 9 | VSS (EP) | Ground pin — exposed pad (heat dissipation) |
Protections
Over-current protection with latch. Triggers at 1.65A or 2× programmable limit.
Over-voltage protection. Shuts off H-bridge above 24V; auto-resumes below 23V.
Under-voltage lockout. Disables all internal logic below 8V threshold.
Two selectable TSD modes: 150°C or 175°C error; 100°C or 125°C alarm.
Rotor lock detection with programmable retry interval 0–6s.
Programmable overload limit 0.10–1.65A in 0.05A steps via GUI.
iT8500E vs iT1300E
| Parameter | iT8500E New | iT1300E |
|---|---|---|
| Operating voltage | 3.2–18V | 3.5–16V |
| Max. rating voltage | 22V | 20V |
| Continuous current | 0.6A | 0.6A |
| Speed command input | PWM + analog voltage (VSP) | Direct PWM only |
| Flexible speed curve | 4 points | 2 points |
| Speed change algorithm | ACC / DEC slope control | Constant |
| Phase angle compensation | Fixed / linear (lead or lag) | Fixed / auto (lead only) |
| Adjustable waveform | ✓ 16 points | ✓ |
| OTP memory | 2 banks | 2 banks |
| Default operating code | ✓ | — |
| Rotor lock detection | ✓ Programmable | ✓ |
| OCP / OVP / UVP / TSD | ✓ | ✓ |
| Package | DFN3×3-8L | DFN3×3-8L |
Six notes for the application circuit
- C1 must be placed as close as possible to VCC / VSS pins. Recommend ≥ 2.2µF / 25V 0603 capacitor.
- Z1 (TVS diode) is required for hot-plug or strict operating conditions protection. 16–18V TVS preferred.
- RPWM = 1K–1.2KΩ and RFG = 47–100Ω for system ESD/EFT improvement.
- When using external Hall sensor: H1 = iA1188D or equivalent Hall latch IC; C2 = 0.1µF typical.
- D1: recommend 2A / 20–40V Schottky diode.
- PCB layout: place 8 vias (Pad 0.5mm / Hole 0.3mm) under the EP to dissipate heat. Hall sensor position at 0.25×T from stator inner edge.
Full Hall placement and PCB rules are in the ASIC design guide.
Ready to evaluate the iT8500E?
Download the preliminary datasheet, request engineering samples, or contact our FAE team for design support.