ASIC design guide
Reference documentation for hardware engineers designing with inergy SoC cooling fan ASIC ICs. Covers IC-specific features, block diagrams, application schematics, Hall sensor placement rules, and key PCB design considerations.
Feature overview, part by part
The spec line reads package · Hall · supply range · continuous current. Part numbers open the datasheet.
Pick an IC, then click a block
Application circuits use the iT1300E as the reference — confirm pin-out against each part's datasheet.
Place the Hall right and commutation stays clean
SMD Hall IC — lateral
SMD Hall IC placed flat on PCB directly under the rotor rim. PCB surface must clear the rotating magnet by less than 2mm. The sensing element faces upward toward the magnet ring.
Position the Hall sensing element at approximately 0.25 × rotor thickness (T) measured from the inner face of the magnet ring inward.
Embedded ASIC — on-PCB
For embedded-Hall ASICs (iT1300E, iT1300T, iT8321E), the ASIC itself is the Hall element. The IC must be placed on the PCB directly beneath the rotor magnet.
Apply the same 0.25 × T depth rule. Position the IC footprint at the silicon steel stator slot opening for best flux signal quality and minimum stator field interference.
DIP through-hole Hall
A through-hole Hall sensor is inserted perpendicular through the PCB, with the sensing face positioned under the rotor. The component body passes through a PCB hole.
Maximum horizontal offset from rotor edge to Hall sensing element: less than 2mm. Mount at the stator slot opening aligned with the magnet pole center.
Placement rule
Place Hall at the slot opening of the silicon steel stator. Offset toward the wider (thicker) side of the stator tooth. If both sides appear equal, center it on the slot.
Magnetic field levels
Point A: near zero crossing — unreliable. Point B: rising edge — acceptable. Point C: peak region — optimal. Strong stable field ensures reliable commutation triggering at all speeds.
Common errors
Hall near outer stator edge → stator field interference → large current variation. Gap > 2mm → weak field → unreliable commutation at high RPM. Wrong depth → poor SNR → FG jitter.
Six PCB and programming rules
Kick-start tuning
Start Kick-Start Duty at 25% (range: 6.25%–100%). If motor fails to start, increase in small steps. Setting too high may trigger OCP from inrush current at standstill.
OTP programming voltage
When burning OTP using iNLinker Lite (Method A), manually reduce supply to 7.5V before clicking Write IC Info. Using iNGenie (Method B), voltage reduction is automatic.
TVS diode on VCC
Add a TVS diode (e.g. SMF17A, 18V/1W) on the VCC line close to the IC. Clamps back-EMF voltage spikes at commutation transitions. iT1300E uses Z1 = 18V/1W TVS + Z2 = 5.8V zener.
Decoupling capacitors
Place 1µF and 100nF ceramic capacitors as close as possible to the IC VCC pin. A bulk electrolytic on the supply rail reduces switch-on inrush. iT8320E uses an inductor L1 on VCC for EMI suppression.
Buffer vs OTP workflow
All iNGUI tuning changes write to IC Buffer only — never modify OTP until you explicitly burn. Always save a .set file after tuning. Verify full operating range before burning OTP — it is write-once per bank.
FG output pull-up
Add a pull-up resistor (51Ω series + 4.7kΩ pull-up to VCC or 3.3V) on the FG/SDA pin. The 51Ω series resistor limits ESD risk and reduces ringing on the FG line.
Want a second pair of eyes on the layout?
Send the schematic and PCB layout. An FAE will check Hall position, protection parts and OTP settings, and arrange samples.