ASIC Design Guide
Reference documentation for hardware engineers designing with inergy SoC cooling fan ASIC ICs. Covers IC-specific features, block diagrams, application schematics, Hall sensor placement rules, and key PCB design considerations.
IC Family — Feature Overview
- Embedded Hall sensor — no external Hall IC required
- 2-point programmable speed curve
- Adjustable lead angle ±90° (largest range in family)
- Direct PWM speed control 1kHz–100kHz input
- 25K/50kHz selectable output switching frequency
- Cycle-by-cycle current limit with gain select
- TSD · OCP · OVP · UVP all with auto recovery
- Selectable FG / Alarm / RD signal output (8 modes)
- Same SoC as iT1300E in TSOT23-6L footprint
- Ultra-compact for tightest PCB constraints
- Embedded Hall sensor (single-phase BLDC)
- Soft start + kick start both configurable via OTP
- PWM pull-up / pull-down input resistor selectable
- FG output with 8 selectable signal modes
- TSD · OCP · OVP · UVP protection suite
- OTP programmable via iNGUI / iNLinker over I²C
- Same SoC as iT8300S in ultra-compact TSOT23-6L footprint
- Embedded Hall sensor — no external Hall IC required
- Direct PWM speed control 1kHz–100kHz input
- 25K/50kHz selectable output switching frequency
- Cycle-by-cycle current limit with gain select
- TSD · OCP · OVP · UVP all with auto recovery
- Selectable FG / Alarm / RD signal output (8 modes)
- OTP programmable via iNGUI / iNLinker over I²C
- External Hall IC input via dedicated HALL_IN pin
- 3-point multi-breakpoint programmable speed curve
- Adjustable lead angle ±45°
- PWM WaitTime and DeadTime independently configurable
- Zero-current detection commutation (higher efficiency)
- LDO5V output pin for external Hall IC supply
- TSD · OCP · OVP · Lock Detection protection
- Closed-loop PI control: KP and KI adjustable
- Embedded Hall + forward/reverse DIR control pin
- Real-time direction switching unique to iT8321E
- Inner KP + Inner KI gain (open loop mode only)
- 3-point speed curve with up to 3 additional breakpoints
- ACC Slope + DEC Slope configurable (closed loop only)
- FG Output Hall Count: 0, 2, or 3 Hall cycles
- Speed Change Algorithm: Speed Slope Control
- LDO5V output available for system use
- Wide-voltage 3V–28V — 24V industrial fans and automation
- DC VSP analog speed control input: 0.2V–3.3V range
- External Hall IC input with full H-bridge drive
- Driver Strength Select: High or Low slew rate
- ChargePump Frequency: 13MHz or 26MHz selectable
- Low Voltage Kick Duty Compensation feature
- LDO3.3V output pin for system circuit supply
- 3-point speed curve + closed/open loop selectable
- SOP8-EP variant with exposed thermal pad
- Same features as iT8330E with improved heat dissipation
- θJA ~50°C/W with thermal pad to PCB copper
- Suited for higher duty-cycle environments
- Wide-voltage 3–28V for 24V industrial applications
- VSP analog speed control 0.2–3.3V
- OCP · OVP · TSD · LRP full protection suite
- 2-bank OTP programmable
SMD Hall IC placed flat on PCB directly under the rotor rim. PCB surface must clear the rotating magnet by less than 2mm. The sensing element faces upward toward the magnet ring.
Position the Hall sensing element at approximately 0.25 × rotor thickness (T) measured from the inner face of the magnet ring inward.
For embedded-Hall ASICs (iT1300E, iT1300T, iT8321E), the ASIC itself is the Hall element. The IC must be placed on the PCB directly beneath the rotor magnet.
Apply the same 0.25 × T depth rule. Position the IC footprint at the silicon steel stator slot opening for best flux signal quality and minimum stator field interference.
A through-hole Hall sensor is inserted perpendicular through the PCB, with the sensing face positioned under the rotor. The component body passes through a PCB hole.
Maximum horizontal offset from rotor edge to Hall sensing element: less than 2mm. Mount at the stator slot opening aligned with the magnet pole center.
Place Hall at the slot opening of the silicon steel stator. Offset toward the wider (thicker) side of the stator tooth. If both sides appear equal, center it on the slot.
Point A: near zero crossing — unreliable. Point B: rising edge — acceptable. Point C: peak region — optimal. Strong stable field ensures reliable commutation triggering at all speeds.
Hall near outer stator edge → stator field interference → large current variation. Gap >2mm → weak field → unreliable commutation at high RPM. Wrong depth → poor SNR → FG jitter.